module timing (
    clk, r, en,
    q0, qs, qm
);

  input clk, r, en;
  output wire [3:0] q0, qm;
  output wire [7:0] qs;

  wire co1, co2;

  // 第一个计时器(10进制)
  counter_n #(.n(10), .counter_bits(4)) Div1(
    .clk(clk), .en(en), .r(r), .q(q0), .co(co1)
  );

  bcdcounter #(.modulus(8'h59)) Div2(
    .clk(clk), .en(co1), .r(r), .q(qs), .co(co2)
  );

  counter_n #(.n(10), .counter_bits(4)) Div3(
    .clk(clk), .en(co2), .r(r), .q(qm), .co()
  );
  
endmodule